With continued increases in the density of integrated circuit devices there are greater challenges to achieve performance requirements such as high circuit speed and noise immunity. Random Access Memory (RAM) circuits are often included in systems-on-a chip (SOC's) wherein such is referred to as embedded memory. Maximizing the speed and error immunity of RAM circuits often requires trade-offs with manufacturing costs. The trade-offs are often, for example, a function of device density or the number of photolithographic steps required to produce desired features. Optimization of memory circuit performance must also be in the context of meeting performance requirements necessary for other circuit components and functions of the SOC. It is of interest to find ways to improve memory circuit performance while having minimal or no impact on overall manufacturing costs and SOC performance.
The embedded memory of these systems may include Static RAM (SRAM), Dynamic RAM (DRAM), or Pseudo-SRAM (PSRAM) circuits. SRAM circuits have the fastest read-write access times of all semiconductor random access memory devices. The memory cell in a conventional SRAM circuit consists of cross-coupled inverters with which one of two stable states is selected. The circuit remains in a stable state as long as power is delivered to the memory cell. In addition to requiring significant power, the conventional SRAM cell design includes six field effect or bipolar transistors formed in monocrystalline semiconductor material. In contrast, DRAM cells only require one transistor and a charge-storing capacitor device, requiring less than one third the space of a conventional SRAM cell. Variants of the SRAM cell design have certain of the transistors replaced with high impedance resistors (e.g., >1010 ohms) or thin film transistors in order to reduce the area required on the semiconductor surface.
While DRAM circuits provide the most area efficient memory storage, the time required for read-write operations is much greater than that of SRAM circuits, and DRAM circuits require refresh operations due to leakage of the charge storage capacitor. The refresh operation is normally performed in response to an externally initiated chip-enable refresh signal by which rows of memory cells are sequentially addressed. In contrast, PSRAM circuitry incorporates timer circuits to generate internal (on-chip) signals which automatically perform the sequential refresh of rows of memory cells. PSRAM circuit architecture is based on DRAM cell design, further including logic to effect automatic refresh. Thus a PSRAM circuit incorporates an area efficient DRAM structure to provide SRAM functionality albeit with somewhat slower performance that that of an SRAM circuit. A PSRAM cell is, generally, up to two thirds the size of the smallest SRAM cell.
One of the challenges in the design of embedded memory circuits relates to the amount of charge density which can be stored in capacitor structures such as used for DRAM and PSRAM circuits. As device sizes are scaled to smaller dimensions it is increasingly difficult to provide the level of capacitance needed to accomodate bit line voltage drops of the type encountered in low voltage designs. Relatively high levels of capacitance are also required to avoid loss of information such as may result from soft errors, e.g. radiation induced charges. Manufacturing constraints and charge leakage across relatively thin dielectric materials necessitate other means to increase the amount of charge and the overall capacitance in memory cells of this type. Use of dielectric compounds in lieu of conventional materials such as silicon oxide has so far not proven to be a viable alternative in the volume manufacture of SOC's.
Generally, scaling of DRAM and PSRAM circuits requires a decrease in cell size while sustaining an ability to store nearly the same amount of charge. In the past this has generated the transition from plate capacitors, i.e., planar designs, to cells which accumulate charge along a three-dimensional structure such as a trench. The capacitor structure may be formed within or above the monocrystalline semiconductor material. Even so, continued progress to even higher levels of integration causes charge storage to remain a key challenge in sustaining acceptable memory performance. Accordingly there is need for capacitor structures which allow for higher levels of charge storage while the size of the memory cell is scaled to smaller dimensions.